1. The Field of the Invention
The present invention relates to methods and apparatus for processing incoming video streams, and more particularly, to methods and apparatus for performing a plurality of demultiplex processing operations on one or more incoming video transport streams.
2. Background and Related Art
Advances in the field of digital video and digital video formats have increased the popularity of using digital video to transport video programming to users. Digital video data is transmitted to viewers using transport streams, which contain the encoded digital video data and the information used by transport stream processors to decode the video data so that it can be displayed to the viewers.
A transport stream includes a series of packets representing digital video data. The exact configurations of the data packets are defined by the digital video format used to encode the video programming. Two of the most common formats are digital video broadcast (DVB), which is based on the Moving Pictures Expert Group-2 (MPEG-2) standard, and digital satellite system (DSS) developed by DIRECTV. DVB has 188-byte packets while DSS has 130-byte packets. The packets of the transport stream include a payload in which the digital video data is encoded and a header that includes an identifier so that the transport stream processor can select packets that correspond to a desired program. In DVB, the identifier is called a packet identifier (PID), while in DSS, the identifier is called a service channel identifier (SCID). Each PID/SCID operates to identify packets of the given type.
There can be approximately 20 to 40 different PIDS/SCIDS within a transport stream, which typically includes multiple programs, each being represented by one or more PIDS/SCIDS. For example, a program may have one PID representing all audio packets, a different PID representing all video packets, and another PID representing packets containing processing information. Transport processing includes demultiplexing the packets so as to obtain the packets associated with a desired program and assembling the packets in such a way that a video decompressor can configure the data into a digital video program.
FIG. 1 illustrates a conventional transport stream processor 1. The transport stream processor includes a processor 10, a memory 12, an input/output (I/O) chip block 16, a descrambler 18, a PID filter 20, a direct memory access (DMA) engine 22, and a list 24. Also provided is host communication 14 through which data, including transports stream data, are provided to the transport stream processor.
Packets in the transport stream are received by processor 10 through host communication 14. Packets are then sent to I/O chip block 16, through which the packets are delivered to descrambler 18. Descrambler 18 performs descrambling operations on the incoming transport stream, including application of PID filter 20. PID filter 20 identifies packets having desired packet identifier information. Descrambler 18 then descrambles the information contained in the identified packets.
Once the packets have been descrambled, they are sent back to processor 10 through the I/O chip block 16. Processor 10 performs additional demultiplexing operations and other operations to prepare data for display as video programming. Memory 12 typically comprises a random access memory or a read-only memory. One function of memory 12 is to provide a code space for instructions defining the demultiplexing processing operations to be performed by processor 10.
Once the incoming packets have been filtered, descrambled, and processed, they are transported to DMA engine 22 through the I/O chip block 16. Because packets in the transport stream are not necessarily sequentially ordered, DMA engine 22 transmits packets into list 24. List 24 allows the packets to be sequenced appropriately for video decoding and image rendering operations performed in preparation for displaying the video data to the viewer.
One of the limitations of the conventional transport stream processor of FIG. 1 is that only a single transport stream may be processed at any given time. Additionally, only a single video program maybe decoded from the transport stream at any given time. To overcome these limitations, user systems may be include multiple transport processors for decoding multiple programs from a transport stream or from multiple transport streams.
FIG. 2 illustrates an architecture for processing multiple video programs. Specifically, FIG. 2 illustrates four separate transport stream processors 1a–d. Each transport stream processor 1a–d performs a unique demultiplexing operation on an incoming video transport stream. Moreover, each transport processor 1a–d is an independent system that includes all hardware necessary for processing a transport stream. While the illustrated architecture allows the system to simultaneously process multiple programs from one or more transport streams, the redundancy of architecture makes the apparatus both expensive to manufacture and inefficient in operation.
In view of the above, it is apparent that there is a need for new and improved methods and apparatus for processing a plurality of video programs from one or more transport streams. It is desirable that the method reduce redundancy of architecture and provide streamlined processing and retrieval of digital video packets from the one or more transport streams.